DE2-115 DDR2 Controller

I am not sure at this point if I need to add a PLL for the SDRAM. With the NIOS implementation, the PLL was crucial.

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The clock skew depends on physical characteristics of the DE2-115 board. For proper operation of the SDRAM chip,

it is necessary that its clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds.

This can be accomplished by using a phase-locked loop (PLL) circuit which can be manually created using the MegaWizard plug-in. It can also be created automatically using the Clock Signals IP core provided by the Altera

University Program. We will use the latter method in this tutorial.

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