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address, writedata, readdata, readdatavalid, read_n and write_n are self explaining singals. byteenable_n can be constant '0'. chipselect can be tied to '1' if only your peripheral has access to that SDRAM. slave asserts waitrequest when it is busy.
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wire sdram_avl_address; // sdram_avl.address
wire sdram_avl_byteenable_n; // .byteenable_n
wire sdram_avl_chipselect; // .chipselect
wire sdram_avl_writedata; // .writedata
wire sdram_avl_read_n; // .read_n
wire sdram_avl_write_n; // .write_n
wire sdram_avl_readdata; // .readdata
wire sdram_avl_readdatavalid; // .readdatavalid
wire sdram_avl_waitrequest; // .waitrequest
wire reset_reset_n; // reset.reset_n
Looking at the instantiated code, I think you were right when you said that it is straightforward. I started with DDR2 IP Core which has complicated address signals. The way I see it, the addressing concatenated the rows, columns, and bank which has 13, 10, and 2 bits respectively to create an address signal of 25 bits. Moreover, the write and read data has the same word length as the one in the SDRAM. I'll work this thing out.
Many thanks for your insights sir Linas.
Honored Contributor
