Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

DDR2 Controller for Cyclone II

Hi,

I'm trying to implement a DDR2 Controller on my DE2 Board. For this I used the MegaFunction Wizard and inserted a DDR2 Controller MegaFunction. The example driver created with this simply writes to the memory, then reads it, and reports if it did this correct or not [correct me if I am wrong]. I deleted the example driver - aiming to replace it with my own driver.

When I delete the driver and compile the code - I get an error that the ddr_dqs[0] pin does not feed a clock delay control block - so quartus cannot fit the design on the device.

ddr_dqs is not a part of example driver, but is an IO of the DDR2 controller (which I have left unchanged).

Why then, does this happen? Is it that some file associated with the example driver is not being included? I am clueless.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    If you deleted the example driver but haven't replaced it with your own code yet, then the unconnected local bus side of the controller might be causing too much to synthesize away. If that's the case, it might be enough temporarily to connect the local bus side to top-level device pins (with virtual-pin assignments for them in the Assignment Editor if needed to keep from getting a no-fit from too many pins)

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I will second what Brad is saying. Because there is no logic depending on your DDR2 core, the synthesis tool determines that the core is not needed and optimizes it away.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    True, this is what could be happening.

    So in my top level design, I added input ports for local_addr, local_wdata, local_read_req,

    local_write_req, local_be and local_size.

    These I connected to the IOBanks 1 and 2 in Assignment Editor.

    I still get the same error.

    Any idea what could be going on?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Did you compile successfully with the example driver included in the design? If not, get that working first. Do everything instructed in the MegaCore generation messages (for example, running a .tcl script that makes some necessary assignments). Refer to the walk-through instructions in the MegaCore user guide to see whether there are any steps there that you missed.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    The dqs pins act as both an input and an output. The error you are getting is telling you that the DQS pin is not feeding a delay element. This is something that is used when reading from the DDR2 memory. The DQS signal is delayed so as to center align it with the data and use as a data strobe.

    You still don't have any logic dependent on the READ data coming back from the core. So this portion of the design is still getting synthesized away.

    But again, if you've got the design working with the example, why are you removing the example driver without something to replace it with.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    It was not intuitive to me that the Core Logic may get synthesized away if I did not hook up it's ports to my logic.

    This solved my problem with the "DQS does not feed delay control block" error.

    Thank you very much!

    FPGAkitty
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I'm also getting the same error:

    What I do now is a burst of writes, then a burst of reads from the same adress. I brought some of the read data to extern pins so the compiler wouldn't synthesize my logic away, but I'm still getting this error?

    I'm seeking on this all day long, any help would be appreciated

    thanks
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You can't just connect "some" of the read data to pins.

    Consider this. What is the purpose of putting a DDR2 memory controller in the project if it's not attached to anything? So Quartus in it's intelligence says "Oh these DQ pins don't actually connect to anything in the design; I might as well get rid of them". So it does. Then Quartus flags an error for the DQ logic saying that it's not connected to anything.

    Solution:

    Don't put an unused memory controller in the design. If you want to do a test compile, use the example driver to verify the controller.

    Jake