DDR2 Controller for Cyclone II

The dqs pins act as both an input and an output. The error you are getting is telling you that the DQS pin is not feeding a delay element. This is something that is used when reading from the DDR2 memory. The DQS signal is delayed so as to center align it with the data and use as a data strobe.

You still don't have any logic dependent on the READ data coming back from the core. So this portion of the design is still getting synthesized away.

But again, if you've got the design working with the example, why are you removing the example driver without something to replace it with.

Jake