Forum Discussion
Altera_Forum
Honored Contributor
17 years agoTrue, this is what could be happening.
So in my top level design, I added input ports for local_addr, local_wdata, local_read_req, local_write_req, local_be and local_size. These I connected to the IOBanks 1 and 2 in Assignment Editor. I still get the same error. Any idea what could be going on?