DCFIFO not simulating as expected - no data output on q

Folks,

I believe I have gotten to the bottom of this.. I did notice a few assertion errors being flagged during elaboration,

altera_mf.vhd:47082:17:@0ms:(assertion error): Error! USE_EAB must be ON or OFF.

altera_mf.vhd:47070:17:@0ms:(assertion error): Error! UNDERFLOW_CHECKING must be ON or OFF.

altera_mf.vhd:47076:17:@0ms:(assertion error): Error! OVERFLOW_CHECKING must be ON or OFF.

As seen in my original code, the above generics look to have been set so I discounted the error thinking it was somehow related to synthesis or implementation as these parameters relate to device specifics and I was only running a behavioral simulation.

In my effort to figure this out I proceeded to implement a quick hardware design to prove my above assumption. Much to my disgust, the assertion errors were still coming up. After going through the altera_mf.vhd file (wow.. almost 53000 lines!!) i can see the assert is raised if the uppercase string "ON" or "OFF" is not found. My lower case "on" and "off" doesn't cut the mustard, very simple oversight that cost me a day!