library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

library altera_mf;
use altera_mf.altera_mf_components.all;

entity dcfifo_test is
end dcfifo_test;

architecture rtl of dcfifo_test is
    
    ----------------------------
    --PROCS
    ----------------------------
    procedure p_increment_slv(
        signal r_in  : in  std_logic_vector(7 downto 0);
        signal r_out : out std_logic_vector(7 downto 0)
        ) is
    begin
        r_out <= std_logic_vector(unsigned(r_in) + 16);
    end p_increment_slv;

    ----------------------------
    --CONSTANTS
    ----------------------------
    constant data_width : integer := 8;

    ----------------------------
    --SIGNALS
    ----------------------------
    signal aclr         :    std_logic := '1';
    signal clk          :    std_logic;
    signal wrreq        :    std_logic := '0';
    signal wrfull       :    std_logic;
    signal wrempty      :    std_logic;
    signal wrusedw      :    std_logic_vector(data_width-1 downto 0);
    signal data         :    std_logic_vector(data_width-1 downto 0) := x"10";
    signal rdreq        :    std_logic := '0';
    signal rdfull       :    std_logic;
    signal rdempty      :    std_logic;
    signal rdusedw      :    std_logic_vector(data_width-1 downto 0);
    signal q            :    std_logic_vector(data_width-1 downto 0);
    signal eccstatus    :    std_logic_vector(1 downto 0);   
begin
    
fifo_i : dcfifo
    generic map
        (
            lpm_width               =>  data_width,
            lpm_widthu              =>  data_width,
            lpm_numwords            =>  8,
            intended_device_family  =>  "cyclone v",
            underflow_checking      =>  "on",
            overflow_checking       =>  "on",
            use_eab                 =>  "on",
            clocks_are_synchronized =>  "true",
            read_aclr_synch         => "on",
            write_aclr_synch        => "on",
            add_ram_output_register => "on"
        )
    
    port map
        (
            aclr        =>  aclr,
            wrclk       =>  clk,
            wrreq       =>  wrreq,
            wrfull      =>  wrfull,
            wrempty     =>  wrempty,
            wrusedw     =>  wrusedw,
            data        =>  data,
            rdclk       =>  clk,
            rdreq       =>  rdreq,
            rdfull      =>  rdfull,
            rdempty     =>  rdempty,
            rdusedw     =>  rdusedw,
            q           =>  q,
            eccstatus   =>  eccstatus
        );

--Simple testbench to drive
tb: process 
    begin
        clk <= '0';
        aclr <= '1';
        wait for 10 ns;
        --reset everything
        aclr <= '0';
        
        --write data to fifo
        rdreq <= '0';
        wrreq <= '1';
        wait for 10 ns;
        
        for n in 1 to 7 loop
            clk <= '1';
            p_increment_slv(data, data);
            wait for 10 ns;
            clk <= '0';
            wait for 10 ns;
        end loop;
        
        --Read back data
        wrreq <= '0';   --stop write
        
        for n in 1 to 7 loop
            clk <= '1';
            wait for 10 ns;
            clk <= '0';
            wait for 10 ns;
        end loop;
        
        rdreq <= '1';   --enable read
        for n in 1 to 7 loop
            
            clk <= '1';
            wait for 10 ns;
            clk <= '0';
            wait for 10 ns;
        
        --few extra clocks
        end loop;

             for n in 1 to 7 loop
            clk <= '1';
            wait for 10 ns;
            clk <= '0';
            wait for 10 ns;
        end loop;
        
        if (q = x"11") then wait; --read q just incase being optimised away
        end if;
        wait;

    end process;


end rtl;