DAC with THDB-ADA on DE2-115

If your FPGA output is q[7:0], and signal before DAC is DAC_DA[13:0], try this----------

DAC_DA[13:0]={1'b0, ~q[7], q[6:0], 5'b00000}

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I contect with technical support of THDB-ADA board. They said this board does not support DC output. I think maybe that means, if you want to get a rectangle like waveform, the shape of that will degrade or change.

Thank you very much :)

I'm think I know about this daugher board really well right now :)

The reason why this board doesn't receive the DC signal is that, if you have a look at the supplied schematic, there is a high pass filter (parallel RC) at every input. I calculated it to be 1.592 KHz. So, if someone would like to deal with voice frequency, they have to build a frequency amplifier interface.

The reason why I didn't get this to be solven before is that I was blindly believe their schimatic, in which the output-bit enables are inputs from that daughterboard, lol.

By the way, I'm using VHDL, not Verilog :D

We can discuss about this board if you like :)

Regards,

Tan

I am so glad that there's someone who are working with this daughter board as well and so nice to share experence with me. So, thank you very much.

This daughter board really confused me a lot.

I am designing an OFDM communication system using DE2-115 FPGA and THDB-ADA daughter board. I thought I can use this daughter board to convert 8 bit parral signal to multi-amplitude annalog signal. But I found the output waveform are not rectangle like. Nowadays, I want to add the ADC in this daughter board to see I can can get the same signal after DAC and ADC. But I am not sure whether it can work.

BTW, I am using Verilog and my circuit knowledge is so poor that I sometimes cannot understand the schimatic.

I don't know much about OFDM. As far as I know, it's a system using many sub-carriers to transmit digital information. In case of that, I dont think it is impossible to get multiple frequency signals onto processing by that daughter board. However, the frequency for a carrier using DE2-115 for that ADC abd DAC, in my opinion, are, should be less than 6MHz to create a good waveform.

Here is a trick that I found myself (I'm sure there are at least 1 more using OBUF) that will be useful for you to deal with ADC and DAC on that board.

First, you create 2 25MHz clock by detectting the rising edge and falling edge of your main clock, like:

If risingedge, clockR = not clockR

If fallingedge, clockF = not clockF

Then use your clockF to drive the DAC clocks, Write signals, using clockR to drive ADC and the whole program. This is to avoid the clock skew when sometimes ADC samples first and DAC samples later, and vice versa (try to imagine here, I'm not cery good in explaining, try me if you dont understand)

Then, I'm sure your waveform will get no any distortion (if the output is clocked in your program)

Cheers,

Tan

I also developed an OFDM modem using the DE2-115 and terasic THDB board. I found that the most fool proof method was to look very closely at the pin assignments in the example projects provided with the THDB card, then replicate it perfectly in your project. Once you get the DAC and ADC up and running, it should be fairly straightforward to develop an OFDM module. You must simulate first though. You have almost no hope without simulating first. Do it in a modular fashion. An OFDM MODEM starts with the IFFT. Say you use a 128 subcarrier system, you need to pass to the IFFT 128 real and 128 imaginary samples, one by one. Say you use Binary Phase Shift Keying, each real and imaginary input represents a point on the constellation diagram. For BPSK, each complex point can encode only 1 bit because you set the imaginary input to zero. So you pass in the real input as, say, 1000 or -1000 (in decimal), and the imag input as zero. The IFFT then creates a real and imaginary 128 point time domain waveform which you must multiply by the cosine (for real) and sine (for imaginary) of the carrier frequency. The carrier is easy to generate using a Numerically Controlled Oscillator. Add the two waveforms, filter and send to the DAC.

Then, do the reverse process at the receiver (quadrature multiplication etc), input to FFT. You should get out the same as you put in to the IFFT at the transmitter. For coherent OFDM, the information is in the absolute positioning of the received constellation points, but for a number of reasons, you'll get variations in their positioning. To use coherent OFDM, you must try to get perfect timing and correct for rotations in the channel. If you are developing this system alone with little experience, I would recommend using DIFFERENTIAL encoding, where the information resides not in the absolute position of the received points, but in the difference between neighbouring subcarriers.

To offer you hope, however, all the tools for building an OFDM MODEM are in Quartus, but you need to take it step by step, simulate every step of the way and try to overcome problems one by one (at the transmitter: cyc pre insertion, at the receiver: timing (look at Schmidl Cox), demapping (look at Cordic algorithms). It's not an easy task for one person but it *is* possible.

Hi everyone:

I am trying to use the THDB Board to create a DAC. But I have a problem, I can see my square wave.I tried connecting all the jumpers in the configuration that the manual says but it doesn't work. The assignment pin I think is correct. Could you give a hit to use it??

Thank You

--- Quote Start ---

Hi everyone:

I am trying to use the THDB Board to create a DAC. But I have a problem, I can see my square wave.I tried connecting all the jumpers in the configuration that the manual says but it doesn't work. The assignment pin I think is correct. Could you give a hit to use it??

Thank You

--- Quote End ---

Follow this

your entity should have:

XOUT : out std_logic_vector(13 downto 0);

YOUT : out std_logic_vector(13 downto 0);

-- adc 14 bit data inputs

XIN : in std_logic_vector(13 downto 0);

YIN : in std_logic_vector(13 downto 0);

-- Setup ADC and DAC

DAC_MODE : out std_logic; -- DAC mode, 1 for dual

DAC_WRTA : out std_logic; -- Write signal Channel A

DAC_WRTB : out std_logic; -- Write signal Channel B

ADC_OEA : out std_logic; -- Channel A enable

ADC_OEB : out std_logic; -- Channel b enable

PLL_OUT_ADC : out std_logic_vector(1 downto 0);

PLL_OUT_DAC : out std_logic_vector(1 downto 0)); -- Clock from HSMC

your interface:

--Clock processing---------------------------

process(CLOCK_50)

begin

if falling_edge(CLOCK_50) then

clockF <= not(clockF);

end if;

if rising_edge(CLOCK_50) then

clockR <= not(clockR);

end if;

end process;

--DAC and ADC interface----------------------

PLL_OUT_ADC(0) <= clockR;

PLL_OUT_ADC(1) <= clockR;

PLL_OUT_DAC(0) <= clockF;

PLL_OUT_DAC(1) <= clockF;

DAC_WRTA <= clockF;

DAC_WRTB <= clockF;

DAC_MODE <= '1'; -- Dual mode

ADC_OEA <= '0';

ADC_OEB <= '0';

--your outputs

YOUT <= YIN;;

XOUT <= XIN;

The whole thing should work.

Here is pins the assignment

ADC_OEA Location PIN_T25

ADC_OEB Location PIN_T26

CLOCK_50 Location PIN_Y2

DAC_MODE Location PIN_H24

DAC_WRTA Location PIN_H23

DAC_WRTB Location PIN_M25

PLL_OUT_ADC[0] Location PIN_G23

PLL_OUT_ADC[1] Location PIN_G24

PLL_OUT_DAC[0] Location PIN_V24

PLL_OUT_DAC[1] Location PIN_V23

RESET Location PIN_AB28

XIN[0] Location PIN_T22

XIN[1] Location PIN_T21

XIN[2] Location PIN_R23

XIN[3] Location PIN_R22

XIN[4] Location PIN_R21

XIN[5] Location PIN_P21

XIN[6] Location PIN_P26

XIN[7] Location PIN_P25

XIN[8] Location PIN_N26

XIN[9] Location PIN_N25

XIN[10] Location PIN_L22

XIN[11] Location PIN_L21

XIN[12] Location PIN_U26

XIN[13] Location PIN_U25

XOUT[0] Location PIN_D27

XOUT[1] Location PIN_D28

XOUT[2] Location PIN_E27

XOUT[3] Location PIN_E28

XOUT[4] Location PIN_F27

XOUT[5] Location PIN_F28

XOUT[6] Location PIN_G27

XOUT[7] Location PIN_G28

XOUT[8] Location PIN_K27

XOUT[9] Location PIN_K28

XOUT[10] Location PIN_M27

XOUT[11] Location PIN_M28

XOUT[12] Location PIN_K21

XOUT[13] Location PIN_K22

YIN[0] Location PIN_V22

YIN[1] Location PIN_U22

YIN[2] Location PIN_V28

YIN[3] Location PIN_V27

YIN[4] Location PIN_U28

YIN[5] Location PIN_U27

YIN[6] Location PIN_R28

YIN[7] Location PIN_R27

YIN[8] Location PIN_V26

YIN[9] Location PIN_V25

YIN[10] Location PIN_L28

YIN[11] Location PIN_L27

YIN[12] Location PIN_J26

YIN[13] Location PIN_J25

YOUT[0] Location PIN_F24

YOUT[1] Location PIN_F25

YOUT[2] Location PIN_D26

YOUT[3] Location PIN_C27

YOUT[4] Location PIN_F26

YOUT[5] Location PIN_E26

YOUT[6] Location PIN_G25

YOUT[7] Location PIN_G26

YOUT[8] Location PIN_H25

YOUT[9] Location PIN_H26

YOUT[10] Location PIN_K25

YOUT[11] Location PIN_K26

YOUT[12] Location PIN_L23

YOUT[13] Location PIN_L24

You can use this to simulate a sine wave 2MHz

signal datax_s : std_logic_vector(13 downto 0);

constant len : integer := 100;

type data_array is array(natural range len-1 downto 0) of std_logic_vector(13 downto 0);

signal datax: data_array := (

"10000000000000","10111101101010","11101100000100","11111111101111",

"11110011110100","11001011001111","10010000000010","01010000111000",

"00011101010111","00000010010001","00000110010000","00101000011000",

"01100000001010","10011111110101","11010111100111","11111001101111",

"11111101101110","11100010101000","10101111000111","01101111111101",

"00110100110000","00001100001011","00000000010000","00010011111011",

"01000010010101","01111111111111","10111101101010","11101100000100",

"11111111101111","11110011110100","11001011001111","10010000000010",

"01010000111000","00011101010111","00000010010001","00000110010000",

"00101000011000","01100000001010","10011111110101","11010111100111",

"11111001101111","11111101101110","11100010101000","10101111000111",

"01101111111101","00110100110000","00001100001011","00000000010000",

"00010011111011","01000010010101","10000000000000","10111101101010",

"11101100000100","11111111101111","11110011110100","11001011001111",

"10010000000010","01010000111000","00011101010111","00000010010001",

"00000110010000","00101000011000","01100000001010","10011111110101",

"11010111100111","11111001101111","11111101101110","11100010101000",

"10101111000111","01101111111101","00110100110000","00001100001011",

"00000000010000","00010011111011","01000010010101","01111111111111",

"10111101101010","11101100000100","11111111101111","11110011110100",

"11001011001111","10010000000010","01010000111000","00011101010111",

"00000010010001","00000110010000","00101000011000","01100000001010",

"10011111110101","11010111100111","11111001101111","11111101101110",

"11100010101000","10101111000111","01101111111101","00110100110000",

"00001100001011","00000000010000","00010011111011","01000010010101"); -- 2MHz

create_signal_process: process(RESET,clockR)

begin

if RESET = '1' then

datax_s <= (others => '0');

elsif rising_edge(clockR) then

datax <= datax(len-2 downto 0) & datax(len-1);

datax_s <= datax(len-1);

end if;

XOUT <= datax_s;

end process;

XOUT (DAC channel A) should be a sinewave 2MHz

--- Quote Start ---

Follow this

your entity should have:

XOUT : out std_logic_vector(13 downto 0);

YOUT : out std_logic_vector(13 downto 0);

-- adc 14 bit data inputs

XIN : in std_logic_vector(13 downto 0);

YIN : in std_logic_vector(13 downto 0);

-- Setup ADC and DAC

DAC_MODE : out std_logic; -- DAC mode, 1 for dual

DAC_WRTA : out std_logic; -- Write signal Channel A

DAC_WRTB : out std_logic; -- Write signal Channel B

ADC_OEA : out std_logic; -- Channel A enable

ADC_OEB : out std_logic; -- Channel b enable

PLL_OUT_ADC : out std_logic_vector(1 downto 0);

PLL_OUT_DAC : out std_logic_vector(1 downto 0)); -- Clock from HSMC

your interface:

--Clock processing---------------------------

process(CLOCK_50)

begin

if falling_edge(CLOCK_50) then

clockF <= not(clockF);

end if;

if rising_edge(CLOCK_50) then

clockR <= not(clockR);

end if;

end process;

--DAC and ADC interface----------------------

PLL_OUT_ADC(0) <= clockR;

PLL_OUT_ADC(1) <= clockR;

PLL_OUT_DAC(0) <= clockF;

PLL_OUT_DAC(1) <= clockF;

DAC_WRTA <= clockF;

DAC_WRTB <= clockF;

DAC_MODE <= '1'; -- Dual mode

ADC_OEA <= '0';

ADC_OEB <= '0';

--your outputs

YOUT <= YIN;;

XOUT <= XIN;

The whole thing should work.

Here is pins the assignment

ADC_OEA Location PIN_T25

ADC_OEB Location PIN_T26

CLOCK_50 Location PIN_Y2

DAC_MODE Location PIN_H24

DAC_WRTA Location PIN_H23

DAC_WRTB Location PIN_M25

PLL_OUT_ADC[0] Location PIN_G23

PLL_OUT_ADC[1] Location PIN_G24

PLL_OUT_DAC[0] Location PIN_V24

PLL_OUT_DAC[1] Location PIN_V23

RESET Location PIN_AB28

XIN[0] Location PIN_T22

XIN[1] Location PIN_T21

XIN[2] Location PIN_R23

XIN[3] Location PIN_R22

XIN[4] Location PIN_R21

XIN[5] Location PIN_P21

XIN[6] Location PIN_P26

XIN[7] Location PIN_P25

XIN[8] Location PIN_N26

XIN[9] Location PIN_N25

XIN[10] Location PIN_L22

XIN[11] Location PIN_L21

XIN[12] Location PIN_U26

XIN[13] Location PIN_U25

XOUT[0] Location PIN_D27

XOUT[1] Location PIN_D28

XOUT[2] Location PIN_E27

XOUT[3] Location PIN_E28

XOUT[4] Location PIN_F27

XOUT[5] Location PIN_F28

XOUT[6] Location PIN_G27

XOUT[7] Location PIN_G28

XOUT[8] Location PIN_K27

XOUT[9] Location PIN_K28

XOUT[10] Location PIN_M27

XOUT[11] Location PIN_M28

XOUT[12] Location PIN_K21

XOUT[13] Location PIN_K22

YIN[0] Location PIN_V22

YIN[1] Location PIN_U22

YIN[2] Location PIN_V28

YIN[3] Location PIN_V27

YIN[4] Location PIN_U28

YIN[5] Location PIN_U27

YIN[6] Location PIN_R28

YIN[7] Location PIN_R27

YIN[8] Location PIN_V26

YIN[9] Location PIN_V25

YIN[10] Location PIN_L28

YIN[11] Location PIN_L27

YIN[12] Location PIN_J26

YIN[13] Location PIN_J25

YOUT[0] Location PIN_F24

YOUT[1] Location PIN_F25

YOUT[2] Location PIN_D26

YOUT[3] Location PIN_C27

YOUT[4] Location PIN_F26

YOUT[5] Location PIN_E26

YOUT[6] Location PIN_G25

YOUT[7] Location PIN_G26

YOUT[8] Location PIN_H25

YOUT[9] Location PIN_H26

YOUT[10] Location PIN_K25

YOUT[11] Location PIN_K26

YOUT[12] Location PIN_L23

YOUT[13] Location PIN_L24

--- Quote End ---

I tried to test the program. However it doesnt work. I am using the altera DE2 board and the terasic daughter board. I checked the pin assignment. I cant see anything in the output. Could you help me with this???