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Honored Contributor
12 years agoYou can use this to simulate a sine wave 2MHz
signal datax_s : std_logic_vector(13 downto 0); constant len : integer := 100; type data_array is array(natural range len-1 downto 0) of std_logic_vector(13 downto 0); signal datax: data_array := ( "10000000000000","10111101101010","11101100000100","11111111101111", "11110011110100","11001011001111","10010000000010","01010000111000", "00011101010111","00000010010001","00000110010000","00101000011000", "01100000001010","10011111110101","11010111100111","11111001101111", "11111101101110","11100010101000","10101111000111","01101111111101", "00110100110000","00001100001011","00000000010000","00010011111011", "01000010010101","01111111111111","10111101101010","11101100000100", "11111111101111","11110011110100","11001011001111","10010000000010", "01010000111000","00011101010111","00000010010001","00000110010000", "00101000011000","01100000001010","10011111110101","11010111100111", "11111001101111","11111101101110","11100010101000","10101111000111", "01101111111101","00110100110000","00001100001011","00000000010000", "00010011111011","01000010010101","10000000000000","10111101101010", "11101100000100","11111111101111","11110011110100","11001011001111", "10010000000010","01010000111000","00011101010111","00000010010001", "00000110010000","00101000011000","01100000001010","10011111110101", "11010111100111","11111001101111","11111101101110","11100010101000", "10101111000111","01101111111101","00110100110000","00001100001011", "00000000010000","00010011111011","01000010010101","01111111111111", "10111101101010","11101100000100","11111111101111","11110011110100", "11001011001111","10010000000010","01010000111000","00011101010111", "00000010010001","00000110010000","00101000011000","01100000001010", "10011111110101","11010111100111","11111001101111","11111101101110", "11100010101000","10101111000111","01101111111101","00110100110000", "00001100001011","00000000010000","00010011111011","01000010010101"); -- 2MHz create_signal_process: process(RESET,clockR) begin if RESET = '1' then datax_s <= (others => '0'); elsif rising_edge(clockR) then datax <= datax(len-2 downto 0) & datax(len-1); datax_s <= datax(len-1); end if; XOUT <= datax_s; end process; XOUT (DAC channel A) should be a sinewave 2MHz