cyclone 3 differential input and output definitions

Question

Hi,

I would like to define an 11 lanes bus differential output and a 3 lanes bus differential input on a (cyclone 3) EP3C25F324C8 device. according to the IO specs, the device supports true differential modes only on the side IO banks, which I have used. the protocol I would like to assign is the LVDS one.

I succeeded in defining the output lanes (11) but didn't manage to do so with the input ones.

whenever I assign an input differential pin to a name it automatically assigns the appropriate opposite with an automatic name.

For example, when assigning the name CLK_N to the negative pin of a pair, it assigns to the positive pin the name CLK_N(p) and I want it to be CLK_P.

these are signals that I define in another part of the program.

Thanks for tyhe advices and tips about how to achieve this!

altera_forum · Answer

There's no reason to assign negative pins manually. Assign only the positive pins and let Quartus assign the negative automatically. The differential pair is represented in the HDL design by a single port signal.

In a addition, Cyclone III does provide LVDS receivers on all IO banks, but not true LVDS drivers.

altera_forum · Answer

Hi, I am new to use Altera FPGA. I ran into a problem:

I am using a Cyclone III device, and need to assigne some LVDS differential signal. I have only "positive" signal i/o in my verilog ports and let Quartus II pin planner to create the "negative" signal for me.

So for my signal - MYSIG on A18, I see MYSIG(n) created on B18 for me automatically.

But when I run pin check, I see the error message:

Error: Can't place differential I/O positive pin MYSIG at a differential negative location A18(PAD_437)

Error: Can't place differential I/O negative pin MYSIG(n) at a differential positive location B18(PAD_438)

Don't understand, why Altera create this negative signal for me, but complain there is an Error.

Due to pin compatibility reason, I cannot change the pin out.

Please help!

Thanks,

BZ

altera_forum · Answer

Hi FvM,

thanks for your reply.

So if I understand correctly I need to design a one port signal and define it as a differential one?

Additionally, When I defined the 11 differential outputs, I did so by using the mini lvds protocol, and there Quartus let me assign the differential pairs manually. Do you have any idea about the reason for it?

On a similar note, Could you point me to some good tutorials? I went through the Altera online training, and the google search gave lots of results, some seem ok but most don't.

Thanks,

Yarok

altera_forum · Answer

--- Quote Start ---

I did so by using the mini lvds protocol, and there Quartus let me assign the differential pairs manually.

--- Quote End ---

What do you exactly mean by this? What happens, if you assign the positive pin only? Does Quartus omit the negative pin?

--- Quote Start ---

So for my signal - MYSIG on A18, I see MYSIG(n) created on B18 for me automatically.

--- Quote End ---

According to the error message, the positive pin is B18, not A18. So the reason is that you assigned the wrong pin. You always need to assign the DIFFIO_xxp pin of a differential pair.

altera_forum · Answer

According to the error message, the positive pin is B18, not A18. So the reason is that you assigned the wrong pin. You always need to assign the DIFFIO_xxp pin of a differential pair.

--- Quote End ---

Hi,

I will assign my signal to DIFFIO_xxp if I design from scratch. But in this

case I have to use DIFFIO_xxn to assign my signal port MYSIG. Quartus II automatically create MYSIG(n) on pin DIFFIO_xxp. If so, why the tool also

complain with Error??? It is a little strange.

Is there a option in Quartus to allow me to assign differential signal with inversion: positive port to negative pin, negative port (autogenerated by Quartus) to positive pin?

Thanks a lot !

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cyclone 3 differential input and output definitions

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