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Altera_Forum's avatar
Altera_Forum
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13 years ago

cyclone 3 differential input and output definitions

Hi, I would like to define an 11 lanes bus differential output and a 3 lanes bus differential input on a (cyclone 3) EP3C25F324C8 device. according to the IO specs, the device supports true differ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

There's no reason to assign negative pins manually. Assign only the positive pins and let Quartus assign the negative automatically. The differential pair is represented in the HDL design by a single port signal.

In a addition, Cyclone III does provide LVDS receivers on all IO banks, but not true LVDS drivers.