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Altera_Forum
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13 years ago

cyclone 3 differential input and output definitions

Hi, I would like to define an 11 lanes bus differential output and a 3 lanes bus differential input on a (cyclone 3) EP3C25F324C8 device. according to the IO specs, the device supports true differ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I did so by using the mini lvds protocol, and there Quartus let me assign the differential pairs manually.

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What do you exactly mean by this? What happens, if you assign the positive pin only? Does Quartus omit the negative pin?

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So for my signal - MYSIG on A18, I see MYSIG(n) created on B18 for me automatically.

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According to the error message, the positive pin is B18, not A18. So the reason is that you assigned the wrong pin. You always need to assign the DIFFIO_xxp pin of a differential pair.