cyclone 3 differential input and output definitions

Hi, I am new to use Altera FPGA. I ran into a problem:

I am using a Cyclone III device, and need to assigne some LVDS differential signal. I have only "positive" signal i/o in my verilog ports and let Quartus II pin planner to create the "negative" signal for me.

So for my signal - MYSIG on A18, I see MYSIG(n) created on B18 for me automatically.

But when I run pin check, I see the error message:

Error: Can't place differential I/O positive pin MYSIG at a differential negative location A18(PAD_437)

Error: Can't place differential I/O negative pin MYSIG(n) at a differential positive location B18(PAD_438)

Don't understand, why Altera create this negative signal for me, but complain there is an Error.

Due to pin compatibility reason, I cannot change the pin out.

Please help!

Thanks,

BZ