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Altera_Forum's avatar
Altera_Forum
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13 years ago

cyclone 3 differential input and output definitions

Hi, I would like to define an 11 lanes bus differential output and a 3 lanes bus differential input on a (cyclone 3) EP3C25F324C8 device. according to the IO specs, the device supports true differ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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But in this case I have to use DIFFIO_xxn to assign my signal port MYSIG.

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"I have to" is bad when it refers to impossible things.

I guess, you are trying to fix an error in schematic design? You need to invert the signal somewhere in the logic fabric. If a LVDS receiver/transmitter is connected to the pin, invert the parallel data.