Cyclone 10GX EMIF Won't fit DDR3 X16

Question

I'm trying to implement a X16 DDR3 EMIF in a single bank (2K) of a Cyclone 10GX220. Quartus gives me an error saying that it won't fit.   There are enough pins in the bank if I omit the DM signals. I'm letting Quartus assign the pins, although I've tried manually assigning them and get the same result. If I implement a X8 EMIF I get no complaints from Quartus. Is this really a limitation of the Cyclone 10GX, it requires at least two banks at 1.5V to implement a X16 EMIF?

sstrell · Answer

IIRC, each bank is only 48 pins and 3 of the 4 I/O lanes (12 pins each) must be used for address/command.  That means you can only fit a x8 EMIF in a single bank (DQ + DQS pins in the 4th lane leaving 3 unused pins).  You would need 2 banks for x16.

glees · Answer

This is a huge limitation. I have to assign an entire 2nd bank as 1.5V in order to use just a few pins. 1.5V is not very standard for anything but DDR memory. This leaves that bank fairly useless without external level translators.

I'm beginning to regret my decision to use the Cyclone 10GX.

sstrell · Answer

Unused I/O lanes in a bank can be used for GPIO.  You're not losing the other 36 pins.  EDIT: oh your concern is the voltage.  You don't have any other I/O you need at 1.5.

glees · Answer

Correct, 1.5V is pretty useless.

adzimzm_altera · Answer

Hello GLees,As sstrell has mentioned, you need 2 banks to implement x16 DDR3 memory interface and unused I/O lanes can be used as GPIO.But it's limited to 1.5V.Do you have any further question in this thread?Regards,Adzim

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Cyclone 10GX EMIF Won't fit DDR3 X16

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