Custom IP compilation

I'm assuming you used the Component Editor in Platform Designer to create your custom component.

Something must be incorrect on the Signals & Interfaces tab of the Component Editor. Can you show that? Is your system able to generate manually in Platform Designer? Are there any warning messages in Platform Designer that might provide more info?

Hello,

I have a VHDL file and it's related *_hw.tcl file and import it as New Component in Plateform Designer.

When I generate HDL in Plateform Designer, there is no problem. It is only when I compile the project in Quartus that I have these errors and warnings the first time:

Error: ipbus_qsys_ipbus_avallon_master_1.ipbus_qsys_ipbus_avallon_master_1: Component ipbus_avallon_master 1.0 not found or could not be instantiated
Warning: ipbus_qsys_ipbus_avallon_master_1.interface_requirements: Your system is missing the required interface "avm_m0". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: ipbus_qsys_ipbus_avallon_master_1.interface_requirements: Your system is missing the required interface "clock". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: ipbus_qsys_ipbus_avallon_master_1.interface_requirements: Your system is missing the required interface "reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: ipbus_qsys_ipbus_avallon_master_1.interface_requirements: Your system is missing the required interface "inr_irq0". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: ipbus_qsys_ipbus_avallon_master_1.interface_requirements: Your system is missing the required interface "ipbRead". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: ipbus_qsys_ipbus_avallon_master_1.interface_requirements: Your system is missing the required interface "IpbusWrite". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: ipbus_qsys_ipbus_avallon_master_1: Component type ipbus_avallon_master is not in the library

Best regards,

Antoine

Intel recommends that you move _hw.tcl files and their associated files to an ip/ directory within your Intel® Quartus® Prime project directory.

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/save-an-ip-component-and-create-the.html

If you happen to move the files, point Platform Designer to their location with Tools menu -> Options in Platform Designer GUI. Let me know if it helps.

Regards,

Richard Tan

My VHDL file and _hw.tcl are in ip/ directory with the other *.ip files of the Qsys.

Regards,

Antoine

OK, so you're using Pro. As the errors state, you have created interface requirements for your system and you have not matched those interface requirements. Interface requirements in Pro are a way to build a system from "the outside in" by defining what the exported interfaces to/from the system should be and then building the system in Platform Designer to match those requirements. It's possible that you accidentally created these requirements. As stated in the errors, go to the Interface Requirements tab and see what's there. If you don't require these interfaces to be exported from your system, simply remove the requirements from the tab. If you do need these requirements, then you need to export the interfaces mentioned in the errors.

This is not a custom component issue after all.

Does the reply from sstrell helps in solving your problem?

Regards,

Richard Tan

Hello,

Sorry for my late response. I'm not sure I fully understand this answer.

All signals mentioned in the error are either connected into the QSYS or exported.

What seems strange to me (and my colleagues too) is that there is no problem when I generate HDL in Plateform Designer and they appear only when I compile the project from Quartus and only for first compilation.

Regards,

Antoine

Could you share the design .qar file so we can further investigate on this?

Regards,

Richard Tan

Please find attached the design archive of my project.

Regards,

Antoine

I'm not seeing the warnings you are seeing. All I see is a compilation error because your exported pio interface is 8 bits wide in the system but you instantiated it in top_ipbus_lpsc_extphy as 32 bits wide.