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antoineb's avatar
antoineb
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3 years ago

Custom IP compilation

Hello, I am working on a project using homemade IP instantiated in a PlateformDesigner module. When I try to run compilation, I need to run it 2 or 3 times to succeed. When compiling for the...
antoineb's avatar
antoineb
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3 years ago

Hello,

Sorry for my late response. I'm not sure I fully understand this answer.

All signals mentioned in the error are either connected into the QSYS or exported.

What seems strange to me (and my colleagues too) is that there is no problem when I generate HDL in Plateform Designer and they appear only when I compile the project from Quartus and only for first compilation.

Regards,

Antoine