Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

create bdf Symbol from SV module with Interface using

Trying to use SystemVerilog Interfaces.

Create main.sv file with test sources content:

interface main_bus;

wire [15:0] data;

wire [15:0] address;

logic [ 7:0] slave_instruction;

logic slave_request;

logic bus_grant;

logic bus_request;

logic slave_ready;

logic data_ready;

logic mem_read;

logic mem_write;

endinterface

module processor (

// main_bus interface port

main_bus bus,

// other ports

input logic clock,

input logic resetN,

);

// ... // module functionality code

endmodule

so if I try tool File-Create-CreateSymbolFileForCurrentFile then I'l get error:

error (10016): can't create symbol/include/instantiation/component file for module "processor" because port "bus" has an unsupported type

What I miss? or BDF just doesn't support SystemVerilog Interfaces feature?

P.S. sorry for my English.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    i don't expect you will get away with advanced types like this in a .bdf. there are also limitations with the VHDL types allowed

    you can either port signals out in basic types, or use SystemVerilog instead of .bdf
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    well.. thanks anyway.

    so now I can stop looking for answer and rewrite project and use SV text file in TOP of the project instead bdf.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    BDF support for HDLs is pretty poor, and because you cannot do RTL simulations its best to avoid them anyway.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I think it's possible to use a struct

    or whatever else signals with concatenation at output.

    like that:

    struct { logic [7:0] adr;

    logic [15:0] data;

    logic rd;

    logic wr;

    } bus;

    wire [25:0] bus_out = {bus.data, bus.adr, bus.rd, bus.wr};

    and then use bus_out as module output.

    am I wrong?