create bdf Symbol from SV module with Interface using

Trying to use SystemVerilog Interfaces.

Create main.sv file with test sources content:

interface main_bus;

wire [15:0] data;

wire [15:0] address;

logic [ 7:0] slave_instruction;

logic slave_request;

logic bus_grant;

logic bus_request;

logic slave_ready;

logic data_ready;

logic mem_read;

logic mem_write;

endinterface

module processor (

// main_bus interface port

main_bus bus,

// other ports

input logic clock,

input logic resetN,

);

// ... // module functionality code

endmodule

so if I try tool File-Create-CreateSymbolFileForCurrentFile then I'l get error:

error (10016): can't create symbol/include/instantiation/component file for module "processor" because port "bus" has an unsupported type

What I miss? or BDF just doesn't support SystemVerilog Interfaces feature?

P.S. sorry for my English.