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Altera_Forum's avatar
Altera_Forum
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15 years ago

create bdf Symbol from SV module with Interface using

Trying to use SystemVerilog Interfaces. Create main.sv file with test sources content: interface main_bus; wire [15:0] data; wire [15:0] address; logic [ 7:0] slave_instr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

i don't expect you will get away with advanced types like this in a .bdf. there are also limitations with the VHDL types allowed

you can either port signals out in basic types, or use SystemVerilog instead of .bdf