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Altera_Forum's avatar
Altera_Forum
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15 years ago

create bdf Symbol from SV module with Interface using

Trying to use SystemVerilog Interfaces. Create main.sv file with test sources content: interface main_bus; wire [15:0] data; wire [15:0] address; logic [ 7:0] slave_instr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think it's possible to use a struct

or whatever else signals with concatenation at output.

like that:

struct { logic [7:0] adr;

logic [15:0] data;

logic rd;

logic wr;

} bus;

wire [25:0] bus_out = {bus.data, bus.adr, bus.rd, bus.wr};

and then use bus_out as module output.

am I wrong?