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Occasional Contributor

5 years ago

Solved

CRC error check in verilog

Hi

can anyone help me how to implement an verilog code to check data integrity using CRC for polynomial calculation x11+x8+x7+x6+x4+x3+x1+1.

i want to check data integrity at receiver side.

Thanks

regards

ak6dn
5 years ago
Did you use the solution referenced in your previous post:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Help-needed-for-implementing-CRC-polynomials-in-verilog/m-p/1206976#M66104

Don't start a new post unless you really need to change the subject dramatically.

4 Replies

ak6dn
Regular Contributor
5 years ago
Did you use the solution referenced in your previous post:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Help-needed-for-implementing-CRC-polynomials-in-verilog/m-p/1206976#M66104

Don't start a new post unless you really need to change the subject dramatically.
- ak6dn
  Regular Contributor
  5 years ago
  FYI just for fun I followed the instructions in the previous post for a CRC generator with a data width of 1, polynomial width of 12, with your requested polynomial, and it generated the following results:
  - m_kumar
    Occasional Contributor
    5 years ago
    sir is that logic work for 300Mhz clock source.
    
    thanks in advance