Forum Discussion
Occasional ContributorCRC error check in verilog
Did you use the solution referenced in your previous post:
Don't start a new post unless you really need to change the subject dramatically.
Regular ContributorDid you use the solution referenced in your previous post:
Don't start a new post unless you really need to change the subject dramatically.
- ak6dn
FYI just for fun I followed the instructions in the previous post for a CRC generator with a data width of 1, polynomial width of 12, with your requested polynomial, and it generated the following results:
m_kumarsir is that logic work for 300Mhz clock source.
thanks in advance
- ak6dn
Well, that depends on a lot of things that have not been specified.
Device family, speed grade, layout.
So no way to say at this point.
The implementation is register based with probably just one level, or two at most, in the feedback logic.
So if 300MHz is a valid internal clock for a device, I would say a definite maybe.
