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Altera_Forum's avatar
Altera_Forum
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9 years ago

counter and realization clock - compilation OK / simulation Not OK

Hello dears developpers ,

I'm realizing a little progressive project in VHDL.

I use for that the Quartus II Web edition (v9.1).

Now I have a problem with the clock signal creation... I realized two style of counter (different code) and I get always the same result, when I perform my simulation, there are some glitch on my clock signal.

see the picture

http://www.alteraforum.com/forum/attachment.php?attachmentid=12606&stc=1

I don't know why I have this phenomenon - I explain in french my different issues seens during my developpment here : (https://fixme.ch/wiki/talk:langage_vhdl)

and I placed my complet code in the github store : https://github.com/philouxy/langage-vhdl---exemple-code-/tree/master/project_2_juggler

If you have an idea, I accept gladly.

In advance thank you for your help.

Best regards,

Philippe

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    That simulation is a timing simulation. clk_2Hz is an asynchronous output. It happens because not all of the bits of the counter change at exactly the same time, causing the <= return true/false for a small amount of time. Im guessing that bit 3 is changing quicker than bits 0,1,2, momentarily giving you "1111" when it switches to 8, and is slower than the rest, giving you "1001" when it switches to 12. This will give you the glitches:

    Solution - make clk_2hz_sim a register: 

    
process(CLK_1_8MHZ)
begin
  if rising_edge(CLK_1_8MHZ) then
    if (compteur_num_p <= VAL_MAX_CMPT_DIV_2) then
      clk_2Hz_SIM <= '0';
    else
      clk_2Hz_SIM <= '1';
    end if;
  end if;
end process;

    On another important note - what are you generating this clock for? generating clocks for other logic is bad practice as it is prone to timing problems and glitches (as you can see). You should use clock enables instead.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I'm not sure this is really a clock for digital logic, at 2 Hz, and it's also an output of the RTL? I'm thinking it's really just a pulse that makes the LED segments change... But, yeah, the glitches are real, and it's due to your logic after the flop. Put the assignment to clk_2Hz_SIM in a clocked process.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hello Tricky and Susannah,

    Thank you for your help.

    For the frequency of 2Hz, it's just to do blinking a 7 seg display - but i don't know if there will have a best practise to realize a slow clock

    here my new code with signal synchronisation 

    
	--------------
	-- compteur -- 
	--------------	
	CMPT_ETAT_FUTUR_2HZ : process(compteur_num_p)
		begin 
			if (compteur_num_p >= VAL_MAX_COMPTEUR_2HZ) then
				compteur_num_f <= (others => '0');
			else 
				compteur_num_f <= compteur_num_p + 1;  
			end if; 
	end process; 
	
	CMPT_ETAT_PRESENT_2HZ : process(CLK_1_8MHZ)
		begin 
			if ((CLK_1_8MHZ'event) and (CLK_1_8MHZ = '1')) then 
				compteur_num_p <= compteur_num_f;
			end if; 
	end process; 
	
--	-----------------------------------------
--	-- Horloge 2Hz rapport cyclique de 50% -- 
--	-----------------------------------------
	CLK_2HZ_50P : process (compteur_num_p) 
		begin 
			if rising_edge (CLK_1_8MHZ) then 
				if (compteur_num_f <= VAL_MAX_CMPT_DIV_2) then
					clk_2Hz <= '0';
				else 
					clk_2Hz <= '1'; 
				end if;
			end if; 
	end process; 
	
	clk_2Hz_SIM <= clk_2Hz;

    Still thank for your explanation.

    Best regards,

    Philippe