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Altera_Forum
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9 years ago

counter and realization clock - compilation OK / simulation Not OK

Hello dears developpers , I'm realizing a little progressive project in VHDL. I use for that the Quartus II Web edition (v9.1). Now I have a problem with the clock signal creation......
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I'm not sure this is really a clock for digital logic, at 2 Hz, and it's also an output of the RTL? I'm thinking it's really just a pulse that makes the LED segments change... But, yeah, the glitches are real, and it's due to your logic after the flop. Put the assignment to clk_2Hz_SIM in a clocked process.