counter and realization clock - compilation OK / simulation Not OK

That simulation is a timing simulation. clk_2Hz is an asynchronous output. It happens because not all of the bits of the counter change at exactly the same time, causing the <= return true/false for a small amount of time. Im guessing that bit 3 is changing quicker than bits 0,1,2, momentarily giving you "1111" when it switches to 8, and is slower than the rest, giving you "1001" when it switches to 12. This will give you the glitches:

Solution - make clk_2hz_sim a register:

process(CLK_1_8MHZ)
begin
  if rising_edge(CLK_1_8MHZ) then
    if (compteur_num_p <= VAL_MAX_CMPT_DIV_2) then
      clk_2Hz_SIM <= '0';
    else
      clk_2Hz_SIM <= '1';
    end if;
  end if;
end process;

On another important note - what are you generating this clock for? generating clocks for other logic is bad practice as it is prone to timing problems and glitches (as you can see). You should use clock enables instead.