counter and realization clock - compilation OK / simulation Not OK

Hello Tricky and Susannah,

Thank you for your help.

For the frequency of 2Hz, it's just to do blinking a 7 seg display - but i don't know if there will have a best practise to realize a slow clock

here my new code with signal synchronisation

	--------------
	-- compteur -- 
	--------------	
	CMPT_ETAT_FUTUR_2HZ : process(compteur_num_p)
		begin 
			if (compteur_num_p >= VAL_MAX_COMPTEUR_2HZ) then
				compteur_num_f <= (others => '0');
			else 
				compteur_num_f <= compteur_num_p + 1;  
			end if; 
	end process; 
	
	CMPT_ETAT_PRESENT_2HZ : process(CLK_1_8MHZ)
		begin 
			if ((CLK_1_8MHZ'event) and (CLK_1_8MHZ = '1')) then 
				compteur_num_p <= compteur_num_f;
			end if; 
	end process; 
	
--	-----------------------------------------
--	-- Horloge 2Hz rapport cyclique de 50% -- 
--	-----------------------------------------
	CLK_2HZ_50P : process (compteur_num_p) 
		begin 
			if rising_edge (CLK_1_8MHZ) then 
				if (compteur_num_f <= VAL_MAX_CMPT_DIV_2) then
					clk_2Hz <= '0';
				else 
					clk_2Hz <= '1'; 
				end if;
			end if; 
	end process; 
	
	clk_2Hz_SIM <= clk_2Hz;

Still thank for your explanation.

Best regards,

Philippe