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Altera_Forum's avatar
Altera_Forum
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13 years ago

continuous averaging using VHDL

I have a question related to VHDL programming. I want to calculate the continuous average. My example code is: process (clk, reset) begin if (reset = '1') then state<=idle; out-v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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@kaz

I don't see anything stupid in the simulation. No idea why I am getting this delay now.

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I take it that there is no such delay in simulation but in hardware. Did you see sum building up soon and avg taking values. In that case revise your design and use signaltap.

Check your clocking scheme. Your adc samples should be sampled into filter at 19.5KHz. since your clock is 312KHz I therefore assume your done = '1' is enabling clock at 19.5KHz.