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Honored Contributor
Honored Contributorcontinuous averaging using VHDL
I have a question related to VHDL programming. I want to calculate the continuous average. My example code is:
process (clk, reset)
begin
if (reset = '1') then
state<=idle;
out-v...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- @kaz the counter value becomes zero and I get the adc value on the FPGA very late. I think the process is very slow because of 1024 samples. Is there a way to make it fast? --- Quote End --- 1/1024 is the update rate of avg, this then averaged at this slow rate. That is you wanted and shouldn't be a problem , not even in simulation. What is ADC speed then?
