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Altera_Forum
Honored Contributor
13 years ago@kaz
If I dont put '0', I get the following error. Should I reduce subtractor bits? Error (10344): VHDL expression error at adc_cntrl.vhd(160): expression has 12 elements, but must have 13 elements. Can you tell me how can I use one computation section for both switching between them at input to delay section? Can you modify my code? Many Thanks