Forum Discussion
Constraint clocks of SPI interfa
- 2 years ago
Adding the pins of the Quad SPI IP did not work, but generating another clock like this and constraining the other QSPI ports wrt. this clock seems to work somehow
create_generated_clock -name {qclk_vclk} -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {QSPI_CLK}]
[content removed]
- anonimcs2 years ago
Contributor
Hi @RichardTanSY_Altera ,
The design is already pipelined. But what I wanted to achieve mainly is to learn how to properly set constraints for a design like mine, not making the design more "timing-friendly". So it would be great if you can help me with that, so that I can see whether my design is good or I need adjustments on the RTL.
- RichardT_altera2 years ago
Super Contributor
Hi @anonimcs
I attempted to remove my original post content as I mistakenly posted my response in the wrong forum case. However, it seems you can still see it. Please kindly ignore my previous post.
Regarding your issue, if you're okay with sharing your RTL, could you archive the .qar project (Project > Archive Project) so that I can investigate it further? The project_files.zip file doesn't seem to be compilable.Additionally, could you provide the block diagram of your design?
This will help me understand the overall picture and which path you're trying to constrain.
Regards,
Richard Tan- anonimcs2 years ago
Contributor
Hi Richard,
If you can give me your email address, I can generate and send you my .qar file.