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Altera_Forum's avatar
Altera_Forum
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10 years ago

Connecting different width and clock master to slave in QSYS

Hi Guys,

I have an Axi master which is 256 bit running at 125 Mhz and I want to connect this to an AXI slave which is 128-bit running at 250 Mhz.

How can I do this in Qsys and ensure that what ever logic qsys used to connect these two ports will not effect the throughput ?

Can I just add a clock crossing bridge to connect these two. Will the clock crossing bridge take care of width conversion too ?

Or do I need to make a glue logic which will handle this ?

Please guide me.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    You need to manually insert a clock domain crossing bridge into your Qsys project. It won't be done automatically by QSYS. Extra glue logic isn't needed.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi Galfonz,

    Thanks for the reply. Just to make sure that I understand this correctly:

    Inserting a clock crossing bridge will convert the 256 bit AXI @125 Mhz to 256bit AXI @250 Mhz Right ?

    Now, If i just connect this(slave of clock crossing bridge) 256bit AXi @250 Mhz to my ultimate slave which is 128 bit @250 Mhz, Qsys will automatically do the width conversion right ?

    I am pretty new to Qsys and so I want to ensure that the throughput does not get effected.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I don't think the clock crossing bridge will convert data bus widths. Also, in the latest QSYS I don't see the AXI version of this, only Avalon. I thought there was an AXI version, but perhaps not. QSYS will convert between Avalon and AXI so it shouldn't be a problem to use the Avalon bridge. One suggestion, don't worry about optimization until you have a working interface.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Ok. Thanks Galfonz for the suggestion.

    So i will use a clock crossing bridge to convert 256 bit axi @125 Mhz to 256bit Axi at 250 Mhz. Now I can connect this 256bit Axi @250 Mhz coming from clock crossing bridges master to my ultimate slave which is 128bit@250 Mhz. Qsys must take care of the width adaption between CCB master and ultimate slave.

    Now as you say if there is not AXI port for clock crossing bridge, qsys will convert the original 256bit axi@125Mhz to 256bit MM@125 Mhz and this will further be connected to the slave of CCB.

    Makes sense right ?