Connecting different width and clock master to slave in QSYS

Hi Galfonz,

Thanks for the reply. Just to make sure that I understand this correctly:

Inserting a clock crossing bridge will convert the 256 bit AXI @125 Mhz to 256bit AXI @250 Mhz Right ?

Now, If i just connect this(slave of clock crossing bridge) 256bit AXi @250 Mhz to my ultimate slave which is 128 bit @250 Mhz, Qsys will automatically do the width conversion right ?

I am pretty new to Qsys and so I want to ensure that the throughput does not get effected.