Connecting different width and clock master to slave in QSYS

Ok. Thanks Galfonz for the suggestion.

So i will use a clock crossing bridge to convert 256 bit axi @125 Mhz to 256bit Axi at 250 Mhz. Now I can connect this 256bit Axi @250 Mhz coming from clock crossing bridges master to my ultimate slave which is 128bit@250 Mhz. Qsys must take care of the width adaption between CCB master and ultimate slave.

Now as you say if there is not AXI port for clock crossing bridge, qsys will convert the original 256bit axi@125Mhz to 256bit MM@125 Mhz and this will further be connected to the slave of CCB.

Makes sense right ?