Compiling MegaWizard Functions Together

You need to provide readers of this forum with a little more detail, i.e., your background and knowledge and what you want to do.

Your questions imply that you do not understand how HDL languages work, so first you have to;

1. Learn an HDL language, eg., VHDL or Verilog.

2. Get something basic working, eg., blink an LED using an on-board oscillator

3. Modify the design in (2) to use an ALTPLL statically configured

4. "Improve" the design to dynamically configure the ALTPLL

All of these stages could be implemented in the Modelsim simulator, and then tested in hardware using a low-cost development kit such as the Terasic DE0-nano or the Arrow BeMicro-CV board.

FPGAs are somewhat daunting to start with. Forum members will help provide encouragement :)

Cheers,

Dave

Hi Dave,

Well, actually I have some experience with VHDL and have already done some testing and experimenting with a BeMicro kit. The thing is that Quartus is more complicated than the language itself. Also I'm learning by my self so there is no body I can ask other than on this forum. Most of the time I manage to find my way through the difficulties but some times I get stuck like in this case. I managed to get a ALTPLL working but I want to make it configurable and here is where I need help. I also experimented with other cores and now would like to connect them together. So I'd appreciate if some one can show me the path. Thanks

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Well, actually I have some experience with VHDL and have already done some testing and experimenting with a BeMicro kit.

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Great!

Which BeMicro kit? There are three; BeMicro (with a red PCB ), BeMicro-SDK, and BeMicro-CV.

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The thing is that Quartus is more complicated than the language itself.

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Sure, this goes for all complicated tools :)

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Also I'm learning by my self so there is no body I can ask other than on this forum.

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You're welcome to ask questions here. I was just trying to understand what you had figured out so far.

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Most of the time I manage to find my way through the difficulties but some times I get stuck like in this case. I managed to get a ALTPLL working but I want to make it configurable and here is where I need help.

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There is an ALTPLL_RECONFIG core, have you tried using it?

The main thing you need to understand, is that you should be using Modelsim to start with, and only once you have a testbench working well, then test in hardware.

So, task# 1 for you is to instantiate an ALTPLL_RECONFIG component in a testbench, and then write stimulus to access its serial reconfiguration interface. I think there is an example that comes with the MegaCore user manual ... yep, there are several ...

http://www.altera.com/literature/lit-ug.jsp

Try those examples, and if you get stuck, ask questions.

Cheers,

Dave

Thanks Dave, you gave me the boost I needed. I'm using the red BeMicro.

I found this pdf, http://www.altera.co.uk/literature/tt/tt_my_first_fpga.pdf . I followed the instructions and managed to connect some cores together. Felt great :).

I haven't tried ALTPLL_RECONFIG core as the ALTPLL has an option to add extra configuration pins to the same core and that's where I got stuck. But I'll take a look at the link you posted. I'm sure I'll find the necessary information.

I only used Modelsim once but I'll practice with it too. Thanks for all the help so far. I'll keep you posted.

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Thanks Dave, you gave me the boost I needed.

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Great! Sometimes you just need a little encouragement :)

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I'm using the red BeMicro.

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Ok, I have this board. Its USB-Blaster JTAG interface is non-standard, and sometimes troublesome.

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I found this pdf, http://www.altera.co.uk/literature/tt/tt_my_first_fpga.pdf . I followed the instructions and managed to connect some cores together. Felt great :).

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Excellent. In VHDL, you can put component definitions in packages and then "use" the package, or you can define a component locally.

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I haven't tried ALTPLL_RECONFIG core as the ALTPLL has an option to add extra configuration pins to the same core and that's where I got stuck. But I'll take a look at the link you posted. I'm sure I'll find the necessary information.

I only used Modelsim once but I'll practice with it too. Thanks for all the help so far. I'll keep you posted.

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This thread has a basic Modelsim simulation example

http://www.alteraforum.com/forum/showthread.php?t=45770

Cheers,

Dave

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Excellent. In VHDL, you can put component definitions in packages and then "use" the package, or you can define a component locally.

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Or instantiate directly from the library, meaning any errors are spotted at the compile stage, not the mapping stage (in larger designs, this can save 10+ minutes).

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Can any one please give me some basic explanation on the .mif file please? And in which way can the RECON core be reconfigured on the go? Is it by rewriting to this .mif file or there is a simpler way? Thanks.

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A MIF file is a blob of data, much like an Intel .hex file. Altera use it in several of their IP cores often as a way to configure IP with the correct combination of parameters, eg., consider the PLL core, which contains lots of different registers, one way Altera can avoid end-users incorrectly programming the IP block is to have Quartus generate a .mif file with consistent parameters, and then have the user load the .mif file to reconfigure the core.

I'm not sure if that is exactly how the .mif file is used in this case, but you get the general idea ...

Cheers,

Dave