Compile option not saved (reversed to default)

Quartus std 25.1 / Questa Altrera FPGA Ed. 64 2025.2

My project use systemverilog all designs. launch RTL Simulation/Questa from Quartus ,

Everytime error happen not treated as designs are systemverilog.

Opening "Compile->Compile option->verilog" and chage "default" to "systemverilog" 

then re-load design by "do ***_run_msim_rtl_systemverilog.do" command, no error happens.

But next Questa launch, same error happend and "Compile option" reversed to "default" not saved.