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remov_b4_flight's avatar
remov_b4_flight
Icon for New Contributor rankNew Contributor
5 hours ago

Compile option not saved (reversed to default)

Quartus std 25.1 / Questa Altrera FPGA Ed. 64 2025.2 My project use systemverilog all designs. launch RTL Simulation/Questa from Quartus , Everytime error happen not treated as designs are systemve...
Simulation
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 hours ago

In Quartus, go to Assignments -> Settings -> EDA Tool Settings -> Simulation -> Format for output netlist use SystemVerilog HDL. After recompile and rerun the simulation

  • remov_b4_flight's avatar
    remov_b4_flight
    Icon for New Contributor rankNew Contributor
    31 minutes ago

    Thanks, but that setting has already been configured.