compile my existing projects using scripts

Hi there,

i am a newbie to FPGA and I want to build and compile my existing projects using script. I also went through the Intel Quartus Prime Standard Edition User Guide: Scripting (UG-20187).

On my PC, I am running Quartus Prime Standard Edition 15.1

To see if i understood the process, i started with a simple program using DE10-Nano board.
I used the DE10-Nano System Builder to create a template program that consits of Clock, LED, and Button.
Using qsys GUI, I added CLK, Nios-ii/f, Jtag-UART, onchipmemory, PIO-input and PIO-output. In eclipse i have a simple c program that prints "hello NIOS".

Eclipse, QSys and Verilog compiles successfully without any errors and i can see the "hello NIOS" message on the NIOS console via JTAG.

Now i exported the two tcl files to see if can recreate project the using the scripts.

First TCL file was created in Quartus Prime by pressing Project->Generate Tcl file for Project (filename = "DE10_NANO_Minimum_setup_proj.tcl")
Second TCL file was created in QSys by pressing File->Export System as hw.tcl Component. (filename = "de10_nano_minimum_qsys_hw.tcl")

when i ran the *_hw.tcl Component file in the command prompt i got the following error:

C:\Users\dev\Desktop\DE10_Nano_Custom>qsys-script --script=de10_nano_minimum_qsys_hw.tcl
2023.11.28.01:21:30 Info: Doing: <b>qsys-script --script=de10_nano_minimum_qsys_hw.tcl</b>
2023.11.28.01:21:35 Info: set_module_property NAME de10_nano_minimum_qsys_export
2023.11.28.01:21:35 Error: set_module_property: <b>COMPOSITION_CALLBACK</b> not allowed for <b>EModuleProperty</b>, must be in {[NAME, GENERATION_ID]}
2023.11.28.01:21:35 Info: set_module_property compose
2023.11.28.01:21:35 Error: set_module_property compose: null
2023.11.28.01:21:35 Error: set_module_property: <b>opaque_address_map</b> not allowed for <b>EModuleProperty</b>, must be in {[NAME, GENERATION_ID]}
2023.11.28.01:21:35 Info: set_module_property false
2023.11.28.01:21:35 Error: set_module_property false: null

My questions are:

can i use this method to re-create project from script? if this not the correct method, what method do you suggest to recreate existing project using scripts?
if anyone has done this before can you please provide me with more steps how to achieve this?
how do i fix the above error messages?

below is the content of de10_nano_minimum_qsys_hw.tcl file

package require -exact qsys 15.1

# module properties
set_module_property NAME {de10_nano_minimum_qsys_export}
#set_module_property DISPLAY_NAME {de10_nano_minimum_qsys_export_display}

# default module properties
#set_module_property VERSION {1.0}
#set_module_property GROUP {default group}
#set_module_property DESCRIPTION {default description}
#set_module_property AUTHOR {author}

set_module_property COMPOSITION_CALLBACK compose
set_module_property opaque_address_map false

proc compose { } {
    # Instances and instance parameters
    # (disabled instances are intentionally culled)
    add_instance clk_0 clock_source 15.1
    set_instance_parameter_value clk_0 {clockFrequency} {50000000.0}
    set_instance_parameter_value clk_0 {clockFrequencyKnown} {1}
    set_instance_parameter_value clk_0 {resetSynchronousEdges} {NONE}

    add_instance jtag_uart altera_avalon_jtag_uart 15.1
    set_instance_parameter_value jtag_uart {allowMultipleConnections} {0}
    set_instance_parameter_value jtag_uart {hubInstanceID} {0}
    set_instance_parameter_value jtag_uart {readBufferDepth} {64}
    set_instance_parameter_value jtag_uart {readIRQThreshold} {8}
    set_instance_parameter_value jtag_uart {simInputCharacterStream} {}
    set_instance_parameter_value jtag_uart {simInteractiveOptions} {NO_INTERACTIVE_WINDOWS}
    set_instance_parameter_value jtag_uart {useRegistersForReadBuffer} {0}
    set_instance_parameter_value jtag_uart {useRegistersForWriteBuffer} {0}
    set_instance_parameter_value jtag_uart {useRelativePathForSimFile} {0}
    set_instance_parameter_value jtag_uart {writeBufferDepth} {64}
    set_instance_parameter_value jtag_uart {writeIRQThreshold} {8}

    add_instance nios2_gen2 altera_nios2_gen2 15.1
    set_instance_parameter_value nios2_gen2 {tmr_enabled} {0}
    set_instance_parameter_value nios2_gen2 {setting_disable_tmr_inj} {0}
    set_instance_parameter_value nios2_gen2 {setting_showUnpublishedSettings} {0}
    set_instance_parameter_value nios2_gen2 {setting_showInternalSettings} {0}
    set_instance_parameter_value nios2_gen2 {setting_preciseIllegalMemAccessException} {0}
    set_instance_parameter_value nios2_gen2 {setting_exportPCB} {0}
    set_instance_parameter_value nios2_gen2 {setting_exportdebuginfo} {0}
    set_instance_parameter_value nios2_gen2 {setting_clearXBitsLDNonBypass} {1}
    set_instance_parameter_value nios2_gen2 {setting_bigEndian} {0}
    set_instance_parameter_value nios2_gen2 {setting_export_large_RAMs} {0}
    set_instance_parameter_value nios2_gen2 {setting_asic_enabled} {0}
    set_instance_parameter_value nios2_gen2 {setting_asic_synopsys_translate_on_off} {0}
    set_instance_parameter_value nios2_gen2 {setting_asic_third_party_synthesis} {0}
    set_instance_parameter_value nios2_gen2 {setting_asic_add_scan_mode_input} {0}
    set_instance_parameter_value nios2_gen2 {setting_oci_version} {1}
    set_instance_parameter_value nios2_gen2 {setting_fast_register_read} {0}
    set_instance_parameter_value nios2_gen2 {setting_exportHostDebugPort} {0}
    set_instance_parameter_value nios2_gen2 {setting_oci_export_jtag_signals} {0}
    set_instance_parameter_value nios2_gen2 {setting_avalonDebugPortPresent} {0}
    set_instance_parameter_value nios2_gen2 {setting_alwaysEncrypt} {1}
    set_instance_parameter_value nios2_gen2 {io_regionbase} {0}
    set_instance_parameter_value nios2_gen2 {io_regionsize} {0}
    set_instance_parameter_value nios2_gen2 {setting_support31bitdcachebypass} {1}
    set_instance_parameter_value nios2_gen2 {setting_activateTrace} {0}
    set_instance_parameter_value nios2_gen2 {setting_allow_break_inst} {0}
    set_instance_parameter_value nios2_gen2 {setting_activateTestEndChecker} {0}
    set_instance_parameter_value nios2_gen2 {setting_ecc_sim_test_ports} {0}
    set_instance_parameter_value nios2_gen2 {setting_disableocitrace} {0}
    set_instance_parameter_value nios2_gen2 {setting_activateMonitors} {1}
    set_instance_parameter_value nios2_gen2 {setting_HDLSimCachesCleared} {1}
    set_instance_parameter_value nios2_gen2 {setting_HBreakTest} {0}
    set_instance_parameter_value nios2_gen2 {setting_breakslaveoveride} {0}
    set_instance_parameter_value nios2_gen2 {mpu_useLimit} {0}
    set_instance_parameter_value nios2_gen2 {mpu_enabled} {0}
    set_instance_parameter_value nios2_gen2 {mmu_enabled} {0}
    set_instance_parameter_value nios2_gen2 {mmu_autoAssignTlbPtrSz} {1}
    set_instance_parameter_value nios2_gen2 {cpuReset} {0}
    set_instance_parameter_value nios2_gen2 {resetrequest_enabled} {1}
    set_instance_parameter_value nios2_gen2 {setting_removeRAMinit} {0}
    set_instance_parameter_value nios2_gen2 {setting_shadowRegisterSets} {0}
    set_instance_parameter_value nios2_gen2 {mpu_numOfInstRegion} {8}
    set_instance_parameter_value nios2_gen2 {mpu_numOfDataRegion} {8}
    set_instance_parameter_value nios2_gen2 {mmu_TLBMissExcOffset} {0}
    set_instance_parameter_value nios2_gen2 {resetOffset} {0}
    set_instance_parameter_value nios2_gen2 {exceptionOffset} {32}
    set_instance_parameter_value nios2_gen2 {cpuID} {0}
    set_instance_parameter_value nios2_gen2 {breakOffset} {32}
    set_instance_parameter_value nios2_gen2 {userDefinedSettings} {}
    set_instance_parameter_value nios2_gen2 {tracefilename} {}
    set_instance_parameter_value nios2_gen2 {resetSlave} {onchip_memory2.s1}
    set_instance_parameter_value nios2_gen2 {mmu_TLBMissExcSlave} {None}
    set_instance_parameter_value nios2_gen2 {exceptionSlave} {onchip_memory2.s1}
    set_instance_parameter_value nios2_gen2 {breakSlave} {None}
    set_instance_parameter_value nios2_gen2 {setting_interruptControllerType} {Internal}
    set_instance_parameter_value nios2_gen2 {setting_branchpredictiontype} {Dynamic}
    set_instance_parameter_value nios2_gen2 {setting_bhtPtrSz} {8}
    set_instance_parameter_value nios2_gen2 {cpuArchRev} {1}
    set_instance_parameter_value nios2_gen2 {mul_shift_choice} {0}
    set_instance_parameter_value nios2_gen2 {mul_32_impl} {2}
    set_instance_parameter_value nios2_gen2 {mul_64_impl} {0}
    set_instance_parameter_value nios2_gen2 {shift_rot_impl} {1}
    set_instance_parameter_value nios2_gen2 {dividerType} {no_div}
    set_instance_parameter_value nios2_gen2 {mpu_minInstRegionSize} {12}
    set_instance_parameter_value nios2_gen2 {mpu_minDataRegionSize} {12}
    set_instance_parameter_value nios2_gen2 {mmu_uitlbNumEntries} {4}
    set_instance_parameter_value nios2_gen2 {mmu_udtlbNumEntries} {6}
    set_instance_parameter_value nios2_gen2 {mmu_tlbPtrSz} {7}
    set_instance_parameter_value nios2_gen2 {mmu_tlbNumWays} {16}
    set_instance_parameter_value nios2_gen2 {mmu_processIDNumBits} {8}
    set_instance_parameter_value nios2_gen2 {impl} {Fast}
    set_instance_parameter_value nios2_gen2 {icache_size} {4096}
    set_instance_parameter_value nios2_gen2 {fa_cache_line} {2}
    set_instance_parameter_value nios2_gen2 {fa_cache_linesize} {0}
    set_instance_parameter_value nios2_gen2 {icache_tagramBlockType} {Automatic}
    set_instance_parameter_value nios2_gen2 {icache_ramBlockType} {Automatic}
    set_instance_parameter_value nios2_gen2 {icache_numTCIM} {0}
    set_instance_parameter_value nios2_gen2 {icache_burstType} {None}
    set_instance_parameter_value nios2_gen2 {dcache_bursts} {false}
    set_instance_parameter_value nios2_gen2 {dcache_victim_buf_impl} {ram}
    set_instance_parameter_value nios2_gen2 {dcache_size} {2048}
    set_instance_parameter_value nios2_gen2 {dcache_tagramBlockType} {Automatic}
    set_instance_parameter_value nios2_gen2 {dcache_ramBlockType} {Automatic}
    set_instance_parameter_value nios2_gen2 {dcache_numTCDM} {0}
    set_instance_parameter_value nios2_gen2 {setting_exportvectors} {0}
    set_instance_parameter_value nios2_gen2 {setting_usedesignware} {0}
    set_instance_parameter_value nios2_gen2 {setting_ecc_present} {0}
    set_instance_parameter_value nios2_gen2 {setting_ic_ecc_present} {1}
    set_instance_parameter_value nios2_gen2 {setting_rf_ecc_present} {1}
    set_instance_parameter_value nios2_gen2 {setting_mmu_ecc_present} {1}
    set_instance_parameter_value nios2_gen2 {setting_dc_ecc_present} {1}
    set_instance_parameter_value nios2_gen2 {setting_itcm_ecc_present} {1}
    set_instance_parameter_value nios2_gen2 {setting_dtcm_ecc_present} {1}
    set_instance_parameter_value nios2_gen2 {regfile_ramBlockType} {Automatic}
    set_instance_parameter_value nios2_gen2 {ocimem_ramBlockType} {Automatic}
    set_instance_parameter_value nios2_gen2 {ocimem_ramInit} {0}
    set_instance_parameter_value nios2_gen2 {mmu_ramBlockType} {Automatic}
    set_instance_parameter_value nios2_gen2 {bht_ramBlockType} {Automatic}
    set_instance_parameter_value nios2_gen2 {cdx_enabled} {0}
    set_instance_parameter_value nios2_gen2 {mpx_enabled} {0}
    set_instance_parameter_value nios2_gen2 {debug_enabled} {1}
    set_instance_parameter_value nios2_gen2 {debug_triggerArming} {1}
    set_instance_parameter_value nios2_gen2 {debug_debugReqSignals} {0}
    set_instance_parameter_value nios2_gen2 {debug_assignJtagInstanceID} {0}
    set_instance_parameter_value nios2_gen2 {debug_jtagInstanceID} {0}
    set_instance_parameter_value nios2_gen2 {debug_OCIOnchipTrace} {_128}
    set_instance_parameter_value nios2_gen2 {debug_hwbreakpoint} {0}
    set_instance_parameter_value nios2_gen2 {debug_datatrigger} {0}
    set_instance_parameter_value nios2_gen2 {debug_traceType} {none}
    set_instance_parameter_value nios2_gen2 {debug_traceStorage} {onchip_trace}
    set_instance_parameter_value nios2_gen2 {master_addr_map} {0}
    set_instance_parameter_value nios2_gen2 {instruction_master_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {instruction_master_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {flash_instruction_master_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {flash_instruction_master_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {data_master_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {data_master_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_instruction_master_0_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_instruction_master_0_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_instruction_master_1_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_instruction_master_1_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_instruction_master_2_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_instruction_master_2_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_instruction_master_3_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_instruction_master_3_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_data_master_0_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_data_master_0_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_data_master_1_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_data_master_1_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_data_master_2_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_data_master_2_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_data_master_3_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {tightly_coupled_data_master_3_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {instruction_master_high_performance_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {instruction_master_high_performance_paddr_size} {0.0}
    set_instance_parameter_value nios2_gen2 {data_master_high_performance_paddr_base} {0}
    set_instance_parameter_value nios2_gen2 {data_master_high_performance_paddr_size} {0.0}

    add_instance onchip_memory2 altera_avalon_onchip_memory2 15.1
    set_instance_parameter_value onchip_memory2 {allowInSystemMemoryContentEditor} {0}
    set_instance_parameter_value onchip_memory2 {blockType} {AUTO}
    set_instance_parameter_value onchip_memory2 {dataWidth} {32}
    set_instance_parameter_value onchip_memory2 {dualPort} {0}
    set_instance_parameter_value onchip_memory2 {initMemContent} {1}
    set_instance_parameter_value onchip_memory2 {initializationFileName} {onchip_mem.hex}
    set_instance_parameter_value onchip_memory2 {instanceID} {NONE}
    set_instance_parameter_value onchip_memory2 {memorySize} {204800.0}
    set_instance_parameter_value onchip_memory2 {readDuringWriteMode} {DONT_CARE}
    set_instance_parameter_value onchip_memory2 {simAllowMRAMContentsFile} {0}
    set_instance_parameter_value onchip_memory2 {simMemInitOnlyFilename} {0}
    set_instance_parameter_value onchip_memory2 {singleClockOperation} {0}
    set_instance_parameter_value onchip_memory2 {slave1Latency} {1}
    set_instance_parameter_value onchip_memory2 {slave2Latency} {1}
    set_instance_parameter_value onchip_memory2 {useNonDefaultInitFile} {0}
    set_instance_parameter_value onchip_memory2 {copyInitFile} {0}
    set_instance_parameter_value onchip_memory2 {useShallowMemBlocks} {0}
    set_instance_parameter_value onchip_memory2 {writable} {1}
    set_instance_parameter_value onchip_memory2 {ecc_enabled} {0}
    set_instance_parameter_value onchip_memory2 {resetrequest_enabled} {1}

    add_instance pio_input_switch altera_avalon_pio 15.1
    set_instance_parameter_value pio_input_switch {bitClearingEdgeCapReg} {0}
    set_instance_parameter_value pio_input_switch {bitModifyingOutReg} {0}
    set_instance_parameter_value pio_input_switch {captureEdge} {0}
    set_instance_parameter_value pio_input_switch {direction} {Input}
    set_instance_parameter_value pio_input_switch {edgeType} {RISING}
    set_instance_parameter_value pio_input_switch {generateIRQ} {0}
    set_instance_parameter_value pio_input_switch {irqType} {LEVEL}
    set_instance_parameter_value pio_input_switch {resetValue} {0.0}
    set_instance_parameter_value pio_input_switch {simDoTestBenchWiring} {0}
    set_instance_parameter_value pio_input_switch {simDrivenValue} {0.0}
    set_instance_parameter_value pio_input_switch {width} {2}

    add_instance pio_output_led altera_avalon_pio 15.1
    set_instance_parameter_value pio_output_led {bitClearingEdgeCapReg} {0}
    set_instance_parameter_value pio_output_led {bitModifyingOutReg} {0}
    set_instance_parameter_value pio_output_led {captureEdge} {0}
    set_instance_parameter_value pio_output_led {direction} {Output}
    set_instance_parameter_value pio_output_led {edgeType} {RISING}
    set_instance_parameter_value pio_output_led {generateIRQ} {0}
    set_instance_parameter_value pio_output_led {irqType} {LEVEL}
    set_instance_parameter_value pio_output_led {resetValue} {0.0}
    set_instance_parameter_value pio_output_led {simDoTestBenchWiring} {0}
    set_instance_parameter_value pio_output_led {simDrivenValue} {0.0}
    set_instance_parameter_value pio_output_led {width} {8}

    # connections and connection parameters
    add_connection nios2_gen2.data_master jtag_uart.avalon_jtag_slave avalon
    set_connection_parameter_value nios2_gen2.data_master/jtag_uart.avalon_jtag_slave arbitrationPriority {1}
    set_connection_parameter_value nios2_gen2.data_master/jtag_uart.avalon_jtag_slave baseAddress {0x0000}
    set_connection_parameter_value nios2_gen2.data_master/jtag_uart.avalon_jtag_slave defaultConnection {0}

    add_connection nios2_gen2.data_master nios2_gen2.debug_mem_slave avalon
    set_connection_parameter_value nios2_gen2.data_master/nios2_gen2.debug_mem_slave arbitrationPriority {1}
    set_connection_parameter_value nios2_gen2.data_master/nios2_gen2.debug_mem_slave baseAddress {0x00080800}
    set_connection_parameter_value nios2_gen2.data_master/nios2_gen2.debug_mem_slave defaultConnection {0}

    add_connection nios2_gen2.data_master onchip_memory2.s1 avalon
    set_connection_parameter_value nios2_gen2.data_master/onchip_memory2.s1 arbitrationPriority {1}
    set_connection_parameter_value nios2_gen2.data_master/onchip_memory2.s1 baseAddress {0x00040000}
    set_connection_parameter_value nios2_gen2.data_master/onchip_memory2.s1 defaultConnection {0}

    add_connection nios2_gen2.data_master pio_output_led.s1 avalon
    set_connection_parameter_value nios2_gen2.data_master/pio_output_led.s1 arbitrationPriority {1}
    set_connection_parameter_value nios2_gen2.data_master/pio_output_led.s1 baseAddress {0x00081010}
    set_connection_parameter_value nios2_gen2.data_master/pio_output_led.s1 defaultConnection {0}

    add_connection nios2_gen2.data_master pio_input_switch.s1 avalon
    set_connection_parameter_value nios2_gen2.data_master/pio_input_switch.s1 arbitrationPriority {1}
    set_connection_parameter_value nios2_gen2.data_master/pio_input_switch.s1 baseAddress {0x00081000}
    set_connection_parameter_value nios2_gen2.data_master/pio_input_switch.s1 defaultConnection {0}

    add_connection nios2_gen2.instruction_master nios2_gen2.debug_mem_slave avalon
    set_connection_parameter_value nios2_gen2.instruction_master/nios2_gen2.debug_mem_slave arbitrationPriority {1}
    set_connection_parameter_value nios2_gen2.instruction_master/nios2_gen2.debug_mem_slave baseAddress {0x00080800}
    set_connection_parameter_value nios2_gen2.instruction_master/nios2_gen2.debug_mem_slave defaultConnection {0}

    add_connection nios2_gen2.instruction_master onchip_memory2.s1 avalon
    set_connection_parameter_value nios2_gen2.instruction_master/onchip_memory2.s1 arbitrationPriority {1}
    set_connection_parameter_value nios2_gen2.instruction_master/onchip_memory2.s1 baseAddress {0x00040000}
    set_connection_parameter_value nios2_gen2.instruction_master/onchip_memory2.s1 defaultConnection {0}

    add_connection clk_0.clk jtag_uart.clk clock

    add_connection clk_0.clk nios2_gen2.clk clock

    add_connection clk_0.clk pio_output_led.clk clock

    add_connection clk_0.clk pio_input_switch.clk clock

    add_connection clk_0.clk onchip_memory2.clk1 clock

    add_connection nios2_gen2.irq jtag_uart.irq interrupt
    set_connection_parameter_value nios2_gen2.irq/jtag_uart.irq irqNumber {0}

    add_connection clk_0.clk_reset jtag_uart.reset reset

    add_connection clk_0.clk_reset nios2_gen2.reset reset

    add_connection clk_0.clk_reset pio_output_led.reset reset

    add_connection clk_0.clk_reset pio_input_switch.reset reset

    add_connection clk_0.clk_reset onchip_memory2.reset1 reset

    add_connection nios2_gen2.debug_reset_request pio_output_led.reset reset

    add_connection nios2_gen2.debug_reset_request pio_input_switch.reset reset

    add_connection nios2_gen2.debug_reset_request nios2_gen2.reset reset

    add_connection nios2_gen2.debug_reset_request onchip_memory2.reset1 reset

    # exported interfaces
    add_interface clk clock sink
    set_interface_property clk EXPORT_OF clk_0.clk_in
    add_interface pio_input_switch conduit end
    set_interface_property pio_input_switch EXPORT_OF pio_input_switch.external_connection
    add_interface pio_output_led conduit end
    set_interface_property pio_output_led EXPORT_OF pio_output_led.external_connection
    add_interface reset reset sink
    set_interface_property reset EXPORT_OF clk_0.clk_in_reset

    # interconnect requirements
    set_interconnect_requirement {$system} {qsys_mm.clockCrossingAdapter} {HANDSHAKE}
    set_interconnect_requirement {$system} {qsys_mm.maxAdditionalLatency} {1}
    set_interconnect_requirement {$system} {qsys_mm.enableEccProtection} {FALSE}
    set_interconnect_requirement {$system} {qsys_mm.insertDefaultSlave} {FALSE}
}

below is the content of DE10_NANO_Minimum_setup_proj.tcl file

# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
# devices manufactured by Altera and sold by Altera or its 
# authorized distributors.  Please refer to the applicable 
# agreement for further details.

# Quartus Prime: Generate Tcl File for Project
# File: DE10_NANO_Minimum_setup_proj.tcl
# Generated on: Tue Nov 28 14:56:41 2023

# Load Quartus Prime Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
	if {[string compare $quartus(project) "DE10_NANO_Minimum"]} {
		puts "Project DE10_NANO_Minimum is not open"
		set make_assignments 0
	}
} else {
	# Only open if not already open
	if {[project_exists DE10_NANO_Minimum]} {
		project_open -revision DE10_NANO_Minimum DE10_NANO_Minimum
	} else {
		project_new -revision DE10_NANO_Minimum DE10_NANO_Minimum
	}
	set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
	set_global_assignment -name FAMILY "Cyclone V"
	set_global_assignment -name DEVICE 5CSEBA6U23I7
	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
	set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
	set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:59:11 NOVEMBER 28,2023"
	set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
	set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
	set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
	set_global_assignment -name QIP_FILE de10_nano_minimum_qsys/synthesis/de10_nano_minimum_qsys.qip
	set_global_assignment -name VERILOG_FILE de10_nano_minimum_qsys/synthesis/de10_nano_minimum_qsys.v
	set_global_assignment -name SDC_FILE DE10_NANO_Minimum.SDC
	set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
	set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
	set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
	set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
	set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
	set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
	set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
	set_location_assignment PIN_V11 -to FPGA_CLK1_50
	set_location_assignment PIN_Y13 -to FPGA_CLK2_50
	set_location_assignment PIN_E11 -to FPGA_CLK3_50
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
	set_location_assignment PIN_AH17 -to KEY[0]
	set_location_assignment PIN_AH16 -to KEY[1]
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
	set_location_assignment PIN_W15 -to LED[0]
	set_location_assignment PIN_AA24 -to LED[1]
	set_location_assignment PIN_V16 -to LED[2]
	set_location_assignment PIN_V15 -to LED[3]
	set_location_assignment PIN_AF26 -to LED[4]
	set_location_assignment PIN_AE26 -to LED[5]
	set_location_assignment PIN_Y16 -to LED[6]
	set_location_assignment PIN_AA23 -to LED[7]
	set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

	# Commit assignments
	export_assignments

	# Close project
	if {$need_to_close_project} {
		project_close
	}
}

thank you

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Platform

ShengN_altera
3 years ago
Hi,

The command qsys-script link here https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/generate-a-system-with-qsys-script.html will be used for the qsys .tcl. Then after source the .tcl the command qsys-generate link here https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/qsys-generate-command-line-options.html will be used on .ip and .qsys to generate the .qip file (GUI will be the Generate HDL in platform designer and IP Generation in Compilation Flow window)

Thanks,
Best Regards,
Sheng

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compile my existing projects using scripts

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