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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Combining similar elements to single combo logic cell after Quartus compilation

I have a question:

how i can disable combining similar elements to single combo logic cell after quartus compilation process.

For example: I have a project like screenshot ("1-block_diagram.jpg" in attachment). In this project we have two "Exclusive OR gate" elements. Green rectangle highlighted is default Quartus II logic primitive symbol "Exclusive OR gate" element (from default library). Red highlighted rectangle is "Exclusive OR gate" element as combination AND, OR and NOT gate elements.

After compilation process we have next:

1) In RTL Viewer we can see that all is OK ("2-rtl_viewer.jpg" in attachment).

2) But as we can see in Technology Map Viewer - Post Fitting ("3_technology_map_viewer_post_fitting.jpg" in attachment) - Qartus combine this two "Exclusive OR gate" elements (green and red rectangle highlighted) as single logic combo cell.

And my question again:

how i can disable this combining similar gate elements to single combo logic cell after quartus compilation process. i need this disabling for my task.

QAR archive file in attachment ("archive.qar").

Thanks in advance for any help.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    use the keep synthesis attribute. For schematic designs you have a special buffer, LCELL buffer. Place this buffer in the inputs and the output of the "own made xor" to tell quartus don't mix with the other.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    use the keep synthesis attribute. For schematic designs you have a special buffer, LCELL buffer. Place this buffer in the inputs and the output of the "own made xor" to tell quartus don't mix with the other.

    --- Quote End ---

    to bertulus - Thank you, you absolutely right - my problem was solved.

    ---

    I drew 3 pictures about how we can use synthesis without combining same elements for Schematic/Verilog/VHDL (pictures in attachment).