Combining similar elements to single combo logic cell after Quartus compilation

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use the keep synthesis attribute. For schematic designs you have a special buffer, LCELL buffer. Place this buffer in the inputs and the output of the "own made xor" to tell quartus don't mix with the other.

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to bertulus - Thank you, you absolutely right - my problem was solved.

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I drew 3 pictures about how we can use synthesis without combining same elements for Schematic/Verilog/VHDL (pictures in attachment).