Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Combinational Logic Synthesis and Fitting

Hello,

I am trying to create a delay line using combinational logic, for this attempt XOR gates. (A - connected to the input from before, B - Connected to an Input pin which will be connected to GND)

When I go into the chip planner to see where my XOR gates are placed, only the first one is created. Looking in my Technology mapper, I see that most of the logic was broken down into a more suitable and faster method. In the RTL viewer, I see that the XOR gates are there but I cannot bring them up in the chip planner or anything else.

I need Quartus to synthesis exactly what I am telling it. Really I wish to turn off any and all optimization options for the synthesis and fitting parts of the compilation.

Thanks for any and all help

--Dolk

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    There is no Xor gate in the fabric, so it has to synthesize it. If you want each XOR gate to be in a LUT, the put a "keep" attribute on each LUT signal. Open your VHDL/Verilog file in Quartus and go to Edit -> Insert Template -> VHDL/Verilog -> Synthesis Attributes -> Keep to get an example. For Verilog I know it's:

    (* keep *) wire my_xor;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Delay using logic to me is scary stuff. Anyway, for the VHDL Keep:

    You need this once (I put it just below my global signal declaration)

    ATTRIBUTE keep: boolean;

    And for each signal (where signal_s is your signal name):

    ATTRIBUTE keep of signal_s: SIGNAL is true;

    I would recommend if at all possible to avoid trying to create delay using combinatorial logic and using some sort of synchronous behavior instead.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for all the help, that worked!

    I am using combinational logic, because I only need ns dealy instead of something in the us or higher. Going through an LUT gives me something like 0.302ns of delay.

    --Dolk
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    There is a big problem with using LUT for delays - it is highly dependent on temperature and routing, so the next time you compile it the delay will probably be different.

    If you need to use LUT delays, you have probably designed something wrong in the first place.