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Altera_Forum
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13 years ago

Combinational Logic Synthesis and Fitting

Hello, I am trying to create a delay line using combinational logic, for this attempt XOR gates. (A - connected to the input from before, B - Connected to an Input pin which will be connected...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks for all the help, that worked!

I am using combinational logic, because I only need ns dealy instead of something in the us or higher. Going through an LUT gives me something like 0.302ns of delay.

--Dolk