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Altera_Forum's avatar
Altera_Forum
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13 years ago

Combinational Logic Synthesis and Fitting

Hello, I am trying to create a delay line using combinational logic, for this attempt XOR gates. (A - connected to the input from before, B - Connected to an Input pin which will be connected...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

There is a big problem with using LUT for delays - it is highly dependent on temperature and routing, so the next time you compile it the delay will probably be different.

If you need to use LUT delays, you have probably designed something wrong in the first place.