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Altera_Forum's avatar
Altera_Forum
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13 years ago

Combinational Logic Synthesis and Fitting

Hello, I am trying to create a delay line using combinational logic, for this attempt XOR gates. (A - connected to the input from before, B - Connected to an Input pin which will be connected...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

There is no Xor gate in the fabric, so it has to synthesize it. If you want each XOR gate to be in a LUT, the put a "keep" attribute on each LUT signal. Open your VHDL/Verilog file in Quartus and go to Edit -> Insert Template -> VHDL/Verilog -> Synthesis Attributes -> Keep to get an example. For Verilog I know it's:

(* keep *) wire my_xor;