Combinational Logic Synthesis and Fitting

Delay using logic to me is scary stuff. Anyway, for the VHDL Keep:

You need this once (I put it just below my global signal declaration)

ATTRIBUTE keep: boolean;

And for each signal (where signal_s is your signal name):

ATTRIBUTE keep of signal_s: SIGNAL is true;

I would recommend if at all possible to avoid trying to create delay using combinatorial logic and using some sort of synchronous behavior instead.