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Ajas's avatar
Ajas
Icon for New Contributor rankNew Contributor
5 years ago

Clock tree synthesis failed in Stratix 10 E-Tile FPGA

Hi,

I am developing a design based on Stratix 10 E-Tile Ethernet FPGA IP. I am using two instances of E-Tile Ethernet core in the design. During place stage, getting error message as ,

Error (18902): Clock tree synthesis failed for signal

and also suggestion as

Info (19957): Clock trees are sized automatically to reach fan-out locations from Early Placement. To see the current fan-out placement, locate any of the signals below in Chip Planner and use the Generate Fan-Out Connections command.
Info (19942): The following clock trees are routing to a region that overlaps the failing signal. To reduce congestion try disabling promotion or providing clock region constraints for clocks in this region.

If the clock region is defined in Assignment editor, error is thrown as Corresponding logic is placed outside of clock region.

If Global assignment is turned off, error is thrown as the particular clock should be routed as a global resource.

Any suggestions to overcome the error would be much helpful.

Thanks,

Ajas.

5 Replies

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    You may review whether any of these competing signals can be moved to a region that does not overlap with the failing signal. If so, apply a Clock Region constraint on the signal source, or a Place Region constraint on the complete fan-out of that signal, to change where the clock tree will be routed.


    Thanks

    Best regards,

    KhaiY


    • Ajas's avatar
      Ajas
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi Khai,

      Thank you for the response.

      I tried logic lock region, still the error did not resolve.

      When clock region constraint is applied, tool thrown an error that the logic is placed in a different region than the clock constrained region so that the clock could not be mapped.

      I also notice one thing. the tool reports about 200 clocks, where as we use only the recovered clock output (clk_rec/pll_div) from the E-Tile core. I think all the E-tile Ethernet IP logic will be in the hard core and that will not be routed in clock network of FPGA fabric. so not sure why these clocks many are reported.

      is there some setting that I am missing leads to this scenario? Any suggestions would be helpful.

      Thanks,

      Asan.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi Asan,

    Could you share the design QAR for investigation? To generate the QAR file, click on Project > Archive Project > Archive

    Thanks

    Best regards,

    KhaiY


    • Ajas's avatar
      Ajas
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi Khai,

      I am unable to share the design QAR due to proprietary IP blocks in the design. I was able to resolve the error with the changes in clock assignments.

      Earlier I was using recovered clock from all the channels. Now, I changed it to only one channel and use it for all the corresponding logic.

      Thanks,

      Asan.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi Asan,


    Thanks for sharing the update. It is glad that you fixed the error.

    I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    Best regards,

    KhaiY