New Contributor
Regular ContributorHi,
You may review whether any of these competing signals can be moved to a region that does not overlap with the failing signal. If so, apply a Clock Region constraint on the signal source, or a Place Region constraint on the complete fan-out of that signal, to change where the clock tree will be routed.
Thanks
Best regards,
KhaiY
New ContributorHi Khai,
Thank you for the response.
I tried logic lock region, still the error did not resolve.
When clock region constraint is applied, tool thrown an error that the logic is placed in a different region than the clock constrained region so that the clock could not be mapped.
I also notice one thing. the tool reports about 200 clocks, where as we use only the recovered clock output (clk_rec/pll_div) from the E-Tile core. I think all the E-tile Ethernet IP logic will be in the hard core and that will not be routed in clock network of FPGA fabric. so not sure why these clocks many are reported.
is there some setting that I am missing leads to this scenario? Any suggestions would be helpful.
Thanks,
Asan.
