Forum Discussion

Ajas's avatar
Ajas
Icon for New Contributor rankNew Contributor
6 years ago

Clock tree synthesis failed in Stratix 10 E-Tile FPGA

Hi, I am developing a design based on Stratix 10 E-Tile Ethernet FPGA IP. I am using two instances of E-Tile Ethernet core in the design. During place stage, getting error message as , Error (1...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Asan,


Thanks for sharing the update. It is glad that you fixed the error.

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY