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Ajas's avatar
Ajas
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5 years ago

Clock tree synthesis failed in Stratix 10 E-Tile FPGA

Hi, I am developing a design based on Stratix 10 E-Tile Ethernet FPGA IP. I am using two instances of E-Tile Ethernet core in the design. During place stage, getting error message as , Error (1...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Asan,

Could you share the design QAR for investigation? To generate the QAR file, click on Project > Archive Project > Archive

Thanks

Best regards,

KhaiY


Ajas's avatar
Ajas
Icon for New Contributor rankNew Contributor
5 years ago

Hi Khai,

I am unable to share the design QAR due to proprietary IP blocks in the design. I was able to resolve the error with the changes in clock assignments.

Earlier I was using recovered clock from all the channels. Now, I changed it to only one channel and use it for all the corresponding logic.

Thanks,

Asan.