Clock enable design meets timing, but fails runtime

I have a 250Mhz clock generating a 125Mhz clock enable. All the logic runs of the 250Mhz with the 125Mhz clock enable at all registers. The design meets timing, but I see mixed results during runtime. SignalTap data looks inncorect and I see mixed results between compiles. For example, I'll post a snippet of code and the failing SignalTap screen shot.

The SignalTap shows the terminal_cnt changing on the rising and faling edge of the clk_125_ce, but some SignalTap samples will show the terminal_cnt changing only on the rising edge. The clock enable isn't working... The terminal counter doesn't even count by ones, it's all over the place.

It appears that the clk_125_ce isn't meeting timing or has place and route issue..... I'm completely stumped and this shouldn't be so difficult. Issues like this appear anywhere the clk_125_ce is used.

Code...

process (clk_250, reset, enable) begin

if clk_250 = '1' and clk_250'event then

if clk_125_ce = '1' then

if reset = '1' or enable = '0' then

terminal_cnt <= (others => '1');

else

if reg_write_1 = '1' then

terminal_cnt <= data_in(31 downto 0);

else

terminal_cnt <= terminal_cnt - 1;

end if;

end if;

end if;

end if;

end process;

tc <= '1' when terminal_cnt = "0000000000000000110" else '0';

SignalTap...

https://www.alteraforum.com/forum/attachment.php?attachmentid=9292

Thanks for your advice!