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Are you getting some strange behavior/synthesis results because your enable and reset are in your sensitivity list but being treated synchronously to clk250 inside your process?
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As we all know, sensitivity lists are ignored in synthesis and matter in simulation only if they are missing signals. This is definitely not the problem.
The result doesn't match the claim of succesful timing analysis. Either you managed to cut some pathes in timing analysis, or the timing analysis assumptions are somehow wrong (e.g device speed grade, supply voltage, clock frequency and clock stability).
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